Device Family: Intel® Arria® 10, Intel® Stratix® 10

Type: How-To

Area: EMIF


Version Found: v19.1
Bug ID: 1807511081

Are there any additional PCB layout recommendations when using twin-die DDR4 memory devices ?

Description

Twin-die DDR4 devices have increased capacitance loading for the address, command and memory clock signals, which can adversely affect the signal integrity in a fly-by topology.
By performing board level simulations to optmize the fly-by topology, trace impedance and terminations, a good PCB layout can be achieved.

It is the responsibility of the user to design and verify their PCB layout with board level simulations.

Below are some techniques for improving signal integrity :

  • Fly-by component placement : Compact layouts such as clamshell tend to cause worse reflections. To reduce reflections at the first DRAM, add some additional signal routing between the first and second DRAM compared to the other fly-by routing lengths.
  • PCB trace impedance : Increasing the trace impedance from the first to the last DRAM may help reduce the reflections but be aware that thinner traces can cause PCB fabrication issues.
  • Board simulation models : Verify the IBIS model correlation accuracy with your memory vendor and find out if the package loss is modeled. HSPICE simulation models may be more accurate.
  • Terminations : Experiment with the values of the parallel terminations to VTT.

If memory test errors are seen during hardware testing which are suspected to be due to address/command signal integrity, a useful technique to confirm this is to probe the alert_n signal with an oscillcoscope and look for a falling edge after the memory has calibrated. A parity error on the address/command signals causes alert_n to pulse low.

Workaround/Fix