Device Family: Intel® Arria® 10, Intel® Stratix® 10

Type: Answers

Area: EMIF


Last Modified: September 25, 2018
Version Found: v18.0
Bug ID: FB: 365354;
IP: Arria 10 External Memory Interfaces, Stratix 10 External Memory Interfaces

What is the behavior of the traffic generator status signals in the Intel® Arria® 10 and the Intel Stratix® 10 EMIF IP example design?

Description

The traffic_gen_pass signal will go high if there are no bit errors, and the test loops for a specific number of cycles.  In the infinite loop test mode, the traffic_gen_pass signal will never go high.

The traffic_gen_fail signal goes high whenever a pnf_per_bit (pnf = pass not fail) signal goes low,  regardless of how many loops the test runs.

The traffic_gen_timeout signal goes high when there is a timeout due to a problem with the traffic generator.

All traffic generator status signals will remain low if the interface fails calibration.