Device Family: Intel® Arria® 10, Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: EMIF


Last Modified: January 30, 2018
Version Found: v17.1
Bug ID: FB: 531779 127216;
IP: Arria 10 External Memory Interfaces, Stratix 10 External Memory Interfaces

Why is the tRTP timing parameter box missing from the Intel® Stratix® 10 and Intel Arria® 10 EMIF IP GUIs?

Description

The tWR and tRTP parameters share the same DDR4 MR0 mode register bits.  Once the tWR parameter is set, the tRTP parameter is set automatically because the tWR and the tRTP relationship is fixed.

  

Workaround/Fix