Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX

Type: Answers

Area: EMIF


IP: Arria 10 External Memory Interfaces, Altera PHYLite for Parallel Interfaces

Why does the PHYLite IP example design fail during the Intel® Quartus® Prime fitter when using OCT with calibration?

Description

You may encounter a similar error as shown below when you attempt to fit the PHYLite example design with OCT calibration and without any pin location assignments.

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter.

This error occurs because when you compile the design without pin location assignments, the fitter attempts to place the PHYLite pins into a 3V IO Bank which does not support OCT with calibration. 

Workaround/Fix

Manually assign the PHYLite pins to any of the LVDS I/O banks which support OCT with calibration. For example, assign the data pins to I/O bank 3C of the device in the QSF file as shown below:

set_location_assignment IOBANK_3C -to group_0_io_interface_conduit_end_io_data_io[*]

This problem will be fixed in a future version of the Intel® Quartus® Prime software.