Device Family: Intel® Arria® 10, Intel® Stratix® 10

Type: Answers

Area: EMIF


Last Modified: June 05, 2018
Version Found: v16.0
Bug ID: FB: 445265;
Document ID: UG-S10EMI
Document Version Found: October 31, 2016
Document Version Fixed: September 30, 2019
IP: Arria 10 External Memory Interfaces, Stratix 10 External Memory Interfaces

Why doesn't the Intel® Arria® 10 or the Intel Stratix® 10 DQ/DQS x4 configuration follow the pin-out placement documentation and the DQ/DQS Pins view in the Intel Quartus® Prime Pin Planner?

Description

When the EMIF IP is configured as DDR3 or DDR4 with x4 DQ/DQS groups, the Quartus® Prime may automatically assign DQ pins to pin locations that don't follow the x4 DQ/DQS groups defined in the device pin-out files.

Workaround/Fix

In the Intel® Arria® 10 or Intel Stratix® 10 I/O architecture for x4 DQ/DQS configuration, it is legal to assign a DQ pin to any DQ I/O location within a x12 I/O lane.