Device Family: Intel® Arria® 10, Intel® Stratix® 10

Type: Answers

Area: EMIF


Bug ID: FB: 1408301693;
IP: Arria 10 External Memory Interfaces, Stratix 10 External Memory Interfaces

What information does the Efficiency Monitor display in the EMIF Toolkit?

Description

The Efficiency Monitor feature in the EMIF Toolkit measures the efficiency on the Avalon interface.  It accepts Avalon signals from a master and sends the commands downstream to a slave without modifying anything on the interface; it is basically an Avalon bridge between the master and the slave and it measures efficiency on this bridge.

 

 

The Efficiency Monitor reports these metrics about the Avalon bus:

Metric

Interpretation

Efficiency Monitor Cycle Count   

Clock cycle counter for the Efficiency Monitor. Lists the number of clock cycles elapsed before the Efficiency Monitor stopped.

 

If this is a 32-bit signal, it will be equal to 2^32 when the efficiency monitor's status is:

"Stopped: Counter saturation"

Transfer Count   Counts any read or write data transfer cycles, where wait request is low.
Write Count  Counts write requests, including those during bursts.
Read Count Counts read requests (not during bursts).
Read Burst Count Counts read requests (total burst requests).
Non-Transfer Cycle Waitrequest Count    Counts Non-Transfer Cycles (NTC) due to slave wait request high, which a read or a write command are issued by master.
Non-Transfer Cycle No Readdatavalid Count  Counts Non-Transfer Cycles (NTC) due to slave not having read data.
Non-Transfer Cycle Master Write Idle Count Counts Non-Transfer Cycles (NTC) within a write burst - due to master not issuing a command.
Non-Transfer Cycle Master Idle Count Counts Non-Transfer Cycles (NTC) due to master not issuing command any time (i.e. if not read or write request from master).
System Efficiency  (Transfer Count) / (Total Cycles)
System Efficiency (During user access)  

(Transfer Count) / (Cycles where a transaction is in progress or pending)

= (Transfer Count) / ( (Total Cycles) - (NTC Master Idle Count) + (NTC Master Write Idle Count) )

Minimum Read Latency    The lowest read latency value.
Maximum Read Latency   The highest read latency value.
Average Read Latency   (Total Read Latency) / (Read Count)