When using the Intel® Arria® 10 or Intel® Stratix® 10 devices DDR3 or DDR4 EMIF IP, if the FPGA I/O tab parameter options > Address/Command > Slew Rate and Memory Clock > Slew Rate are set to different values, this warning message is seen:
Warning: .emif_0: When the address/command signals and the memory clock signals do not use the same slew rate setting, signals using the "Slow" setting are delayed relative to signals using "Fast" setting. For accurate timing analysis, you must perform I/O simulation and manually include the delay as board skew. To avoid the issue, use the same slew rate setting for both address/command signals and memory clock signals whenever possible.
This warning only applies to board level simulations and does not require any delay adjustments in the PCB design or IP Board tab parameter settings.
For optimum timing margins, the general recommendation is to use fast slew rates for both address/command signals and the memory clock, and external terminations to ensure good signal integrity.
In board simulations, using fast slew rates may show a perceived signal integrity issue such as reflections or a non-monotonic waveform in the SSTL I/O switching threshold region, resulting in a designer considering slow slew rate options for either the address/command signal or memory clock or both. Typically this may be seen on address/command signals in DIMM configurations where there is limited opportunity to modify the signal terminations.