Device Family: Intel® Arria® 10, Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: EMIF


Version Found: v16.1
Bug ID: FB: 1806662575;
IP: Arria 10 External Memory Interfaces, Stratix 10 External Memory Interfaces

Warning: When the address/command signals and the memory clock signals do not use the same slew rate setting, signals using the "Slow" setting are delayed relative to signals using "Fast" setting

Description

When using the Intel® Arria® 10 or Intel® Stratix® 10 devices DDR3 or DDR4 EMIF IP, if the FPGA I/O tab parameter options > Address/Command > Slew Rate and Memory Clock > Slew Rate are set to different values, this warning message is seen:

Warning: .emif_0: When the address/command signals and the memory clock signals do not use the same slew rate setting, signals using the "Slow" setting are delayed relative to signals using "Fast" setting. For accurate timing analysis, you must perform I/O simulation and manually include the delay as board skew. To avoid the issue, use the same slew rate setting for both address/command signals and memory clock signals whenever possible.

This warning only applies to board level simulations and does not require any delay adjustments in the PCB design or IP Board tab parameter settings.

For optimum timing margins, the general recommendation is to use fast slew rates for both address/command signals and the memory clock, and external terminations to ensure good signal integrity.

In board simulations, using fast slew rates may show a perceived signal integrity issue such as reflections or a non-monotonic waveform in the SSTL I/O switching threshold region, resulting in a designer considering slow slew rate options for either the address/command signal or memory clock or both.  Typically this may be seen on address/command signals in DIMM configurations where there is limited opportunity to modify the signal terminations.

Workaround/Fix

Due to limitations of the IBIS model correlation tolerance and in the accuracy of the board model in simulation, the fast slew rate signal integrity issue may only be seen only in simulations and not in hardware operation.

If a signal integrity issue is observed in simulations with fast slew rate, it is recommended to measure the same signal at the same place in hardware with an oscilloscope to verify if the signal integrity issue is also seen in hardware operation. If it is, then using different slew rates for the address/command signals and clock is still a valid approach and the address/command calibration stage will help to improve the address/command to clock setup and hold time margins.