Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: EMIF


Version Found: v16.1
Bug ID: FB: 604165;
IP: Arria 10 External Memory Interfaces, Stratix 10 External Memory Interfaces

How long does it take for the Intel® PHYLite IP output delay to take effect when performing dynamic reconfiguration?

Description

The time for the Intel® PHYLite IP output delay to take effect after writing a new value to the register via the Avalon bus, is dependent on the user's configuration.

It will take approximately 50 VCO clock cycles, and Intel recommends that you perform an RTL simulation to obtain accurate timing which will correlate with the hardware operation. The output signal will not glitch.

Workaround/Fix