Device Family: Intel® Arria® 10, Intel® Cyclone® 10, Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: EMIF


Last Modified: January 31, 2018
Version Found: v16.1
Bug ID: FB: 533317;
IP: Stratix 10 External Memory Interfaces, Arria 10 External Memory Interfaces

How is it determined if I/O banks are adjacent for External Memory Interface pin-outs in Intel® Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 FPGAs?

Description

External memory interfaces implemented in Intel® Stratix® 10, Intel Arria® 10 or Intel Cyclone® 10 devices which require more than one I/O bank must be placed in adjacent I/O banks. An adjacent I/O bank is defined as an I/O bank with the same column number and a letter which is either before or after the respective I/O bank letter in the A-Z system.


Refer to the Modular I/O banks section of the Device Handbook I/O chapter or the General Purpose I/O User Guide of the Series 10 Device Family you are using. There are tables of the device parts in different packages indicating which I/O banks are used and how many pins are bonded out.

All I/O banks shown in the same I/O column are adjacent, unless a '-' symbol is shown . A '-' symbol indicates that the bank is not bonded out for the package.
If an I/O bank has less than 48 pins, the letter relationship of the I/O banks is also used to determine if they are adjacent.

The following examples explain these special cases.
For Arria 10 GX480 in package F29 with these I/O banks :
2A  48
2I    -
2J  48

I/O bank 2I is not bonded out, indicating 2A is not adjacent to 2J.

For Arria 10 GX480 in package F34 with these I/O banks :
2A 48
2I  12
2J  48

In this case I/O bank 2I is partially bonded out. The 12 pins in I/O bank 2I are adjacent to 2J but not to 2A. 2A is not adjacent to 2I.

Workaround/Fix

For all external memory interface designs, it is strongly recommended that you implement a project instantiating the External Memory Interface IP with your intended pin-out and verify it compiles successfully and closes timing.
The information on the adjacent I/O banks in the special case examples is scheduled to be added in a future version of the documentation.