Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: How-To

Area: EMIF


Version Found: v16.1
Bug ID: FB: 607515;
IP: Stratix 10 External Memory Interfaces

How can the auto-precharge feature of the Intel® Stratix® 10 DDR4 hard memory controller be used to achieve the highest memory bandwidth?

Description

Regardless of how many DDR4 bank groups have been opened for a series of Avalon-MM accesses to the DDR4 hard controller, the auto-precharge will only take effect on the last beat of the Avalon-MM burst.

Here are 2 examples showing how to achieve the best performance with the auto-precharge feature.

In both cases, use long bursts of sequentially addressed read or write traffic data patterns and the auto-precharge when an access is the last to a memory page. A memory page is defined as a bank group, bank address and row address combination that is opened by a DDR4 activate command.

1) The DDR4 IP is configured with the Efficiency > Address ordering parameter under the Controller tab. You can set this parameter value to CS-CID-Row-Bank-Col-BG or CID-Row-CS-Bank-Col-BG.

Break your Avalon accesses to the DDR4 hard controller into sequentially addressed accesses with a burst size of 1.  4 bank groups will be used and for the last 4 accesses, assert the auto-precharge signal so that all of the bank groups receive read or write with auto-precharge commands. DDR4 devices with x4 and x8 configurations have 4 bank groups. Note that DDR4 x16 devices only have 2 bank groups.

2) The DDR4 IP is configured with the Controller tab parameter > Efficiency > Address ordering set to  CS-BG-Bank-CID-Row-Col

With this address ordering, only one memory page will be opened and Avalon burst accesses with burst sizes greater than one can be used. For the last access in the burst, assert the auto-precharge signal.