Device Family: Arria Series, Cyclone Series, Stratix Series

Intel Software: Quartus II, Quartus Prime

Type: Answers

Area: EMIF


Last Modified: April 04, 2017
IP: Arria 10 External Memory Interfaces, Stratix 10 External Memory Interfaces, memory-interfaces-with-altmemphy, memory-interfaces-with-uniphy

Why do the External Memory Interface DQ and DQS waveforms sometimes have poor signal quality when measured at the FPGA pin on a memory read ?

Description

Even if the DQ and DQS signals are terminated correctly using parallel OCT (FPGA on-chip termination), the read DQ and DQS waveforms may show reflections or non-monotonic behaviour in IBIS model simulations and in hardware measurements when measured at the FPGA pin.
The reason for this is that FPGAs can have a relatively large package delay. Therefore the measurement at the FPGA pin is not at the receiver on the FPGA die where it is important but part way along the transmission line.
Package delay files are available on the Intel website under the Tools Models and Libraries section.

Workaround/Fix

If performing IBIS model simulations, verify that the read DQ and DQS waveforms have good signal integrity when measured at the FPGA die.
If the waveform does not have good signal integrity when measured on hardware with a high quality probe, run the IBIS model simulation with a representative load of the oscilloscope probe. Observe the waveform  at the pin and compare with the hardware measurement.
If they are similar and the IBIS simulation waveform at the die looks good, then the waveform at the die can also be expected to be good.

Refer to this KDB answer for information about the memory data signal IBIS model and dynamic termination. The Intel external memory interface IP uses dynamic OCT on the data signals.