Device Family: Intel® Arria® 10

Type: Answers

Area: EMIF

Last Modified: June 29, 2017
Version Found: v16.1
Version Fixed: v17.0
Bug ID: FB: 439881;
IP: Altera PHYLite for Parallel Interfaces

Why is the parameter “Use core PLL reference clock connection” not available in the PHYLite IP Parameter Editor?


Starting with the Quartus® Prime software version 17.0, the PHYLite IP does not support core PLL reference clock connection. The PHYLite PLL reference clock must be connected to a dedicated reference clock pin.