The DDR4 IP does not require any external VREF rail connected to the VREFB pins of the FPGA I/O banks used for the DQS group signals with I/O standard POD-12.
The VREF is generated internally and is calibrated. In the Quartus® Prime Fitter Report I/O Bank Usage section, it shows there is no VREF requirement.
An external VREF rail of 0.6V is only required for the DDR4 memory device's VREFCA pin and it is recommended to add a decoupling capacitor close to this pin.
VREF for the data signals (DQ, DQS, DM/DBI) is generated internally in the DDR4 memory device and the FPGA DDR4 interface DQS group I/O banks.
Below is additional information on VREF calibration.
The VREF calibration granularity is per I/O lane (a x8 DQS group).
In the EMIF Toolkit calibration report, the FPGA VREF is the VREFIN setting.
DDR4 Memory :
The DDR4 IP supports the per dram addressability functionality so in a multiple memory component interface, each DDR4 component can have a different calibrated VREF value.
In the EMIF Toolkit calibration report, the DDR4 memory VREF is the VREFOUT setting.