Device Family: Stratix® V

Type: Answers

Area: EMIF


Last Modified: May 30, 2017
Version Found: v14.0
Bug ID: FB: 409080 (TRY TO FIX IN 17.1);
IP: DDR3 SDRAM Controller with UniPHY

How do I fix hold timing violations between the c2p_write_clk and the pll_write_clk for a Stratix V DDR3 design?

Description

For a Stratix® V DDR3 UniPHY-based design, you may see hold timing violations on data paths between the c2p_write_clk and the pll_write_clk clock domains.

Workaround/Fix

To resolve these hold timing violations, follow the steps below:

1) In the IP-generated <IP_variation_name>if0_pll0.sv file, set

parameter WRITE_CLK_PHASE = "938 ps"

2) In the IP-generated <IP_variation_name>if0_p0_parameters.tcl file, set

set ::GLOBAL_mem_if_ddr3_emif_example_design_example_if0_p0_pll_phase(PLL_WRITE_CLK) 270.0