Device Family: Intel® Arria® 10, Intel® Stratix® 10

Type: Answers

Area: Component, EMIF

Last Modified: July 06, 2017
Version Found: v17.0
Bug ID: FB: 474381;
IP: Altera PHYLite for Parallel Interfaces

Critical Warning(16643): Found IO_STANDARD assignments found for "ref_clk" pin with multiple values. Using value: "LVDS"


After generating the PHYLITE IP, its pll reference clock is a single-ended input clock with an I/O standard which is determined by the IP General Tab > I/O Settings > I/O standard parameter.
A differential pll reference clock with LVDS I/O standard is also supported and is implemented by adding a QSF I/O standard constraint :
set_instance_assignment -name IO_STANDARD LVDS -to <ref_clk>

This causes the critical warning.


You can safely ignore this critical warning.