Device Family: Intel® Arria® 10

Type: Answers, Documentation

Area: EMIF


Last Modified: January 21, 2017
Version Found: v16.0
Bug ID: FB: 253027;
IP: Arria 10 External Memory Interfaces

Are there any known issues with tCCD_S behavior in the Arria 10 FPGA DDR4 IP?

Description

When using an Arria® 10 quarter-rate DDR4 controller, you may find the CAS_n-to-CAS_n command delay to different bank groups does not meet the tCCD_S parameter setting in the Arria 10 DDR4 Parameter Editor. For example, you may set tCCD_S as 4 in the Parameter Editor but observe 8 cycles in the simulation waveform and hardware. This results in gaps between consecutive read or write transactions and can lower the efficiency of your interface. This extra delay is due to the controller reaching the maximum number of pages it can hold open at once.

Workaround/Fix

Enable “Auto-Precharge Control” by checking the box in the Controller tab in the Arria 10 DDR4 Parameter Editor which allows you to manually close pages that are no longer needed. Toggling this signal precharges the bank and frees up space in the controller to accept new commands.