Last Modified: July 01, 2016
Version Found: v13.0
Bug ID: FB: 385884;

Why are there data errors on the HPS LPDDR2 interface?


Due to a problem in the SoC EDS software version 16.0 and earlier, data errors may be seen on Cyclone® V SoC and Arria® V SoC HPS SDRAM interfaces in LPDDR2 mode.

Hard or soft LPDDR2 interfaces in FPGA logic (non-HPS) are not effected.


To work around this problem in the SoC EDS Software version 16.0 and earlier, follow the steps below.

This workaround manually sets pessimistic values for read-read and write-read turnaround for the Altera HPS SDRAM controller in LPDDR2 mode, which may reduce performance. 

1. Open the following file from your HPS Preloader BSP:  u-boot-socfpga/arch/arm/cpu/armv7/socfpga/sdram.c

2. Add the workaround code below after line 1345 (u-boot 2013):





    /***** START workaround to Set read to read and read to write delay *****/

    debug("manually configuring read to write turnaround delays \n");

    register_offset = 0x501c;

    /* Read original register value */

    reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset);

    reg_value = 0x44400000;

    if (sdram_write_verify(register_offset, reg_value) == 1) {

    status = 1;



    /***** END  Workaround*****/

    /* Restore the SDR PHY Register if valid */

      if (sdr_phy_reg != 0xffffffff)

      writel(sdr_phy_reg, SOCFPGA_SDR_ADDRESS

3. Regenerate the software preloader by running make clean and then followed by running make

This problem is scheduled to be fixed in a future release of the SoC EDS Software.