Device Family: Intel® Arria® 10

Intel Software: Quartus Prime Lite, Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: EMIF

Last Modified: November 26, 2016
Version Found: v16.0 Update 1
Bug ID: FB: 419530;
IP: Arria 10 External Memory Interfaces

Why is my Arria 10 DDR4 design failing compilation in the fitter when I choose "Automatically select a location" for ALERT# pin placement?


If the "Automatically select a location" option is chosen in the Memory Topology/ Topology tab of the Arria® 10 DDR4 IP Editor, the IP will automatically choose a pin assignment for the mem_alert_n signal. If this option is selected and there are conflicting location constraints applied to the mem_alert_n pin, then fitter errors will result during compilation.

The fitter errors will include these messages:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)).

Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.


If you choose to use the "Automatically select a location" option, remove all location assignments and constraints for the mem_alert_n signal in your .QSF file. Intel FPGA recommends manually placing the mem_alert_n signal in the address/command bank for optimum timing margins by choosing the "I/O Lane with Address/Command Pins" option.