Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Type: Answers

Area: Embedded


Last Modified: October 23, 2020
Version Found: v19.3
Bug ID: 18012283614

Why does my Intel Stratix 10 SoC device fail to boot / configure correctly, if I reset the HPS while a configuration event is taking place?

Description

Due to a problem in the Intel® Stratix® 10 Secure Device Manager firmware, the Intel Stratix 10 SoC may fail to boot / configure correctly if an HPS reset event is triggered during a configuration event.  

If Intel Stratix 10 SoC Remote System Update is enabled on the device:  

  • A boot failure during Phase 1 (re-)configuration can trigger a Remote System Update Watchdog event to trigger a reconfiguration event to recover the device.

 

Workaround/Fix

To avoid this problem ensure the following situations do not occur: 

  •  nCONFIG and HPS_COLD_nRESET  SDM IO Pins are both asserted
  •  An HPS reset (HPS_COLD_nRESET SDM IO pin) is issued during an FPGA configuration or re-configuration event.  For example :  In a system using the HPS Boot First flow : While the HPS is (re-)configuring the FPGA Core Logic using a Phase 2 configuration bitstream.

Note:

  • It is not required to cold reset the HPS if the intention is to reconfigure the device using the nConfig signal.  The nConfig event will wipe the entire device, and then reconfigure the device from the selected boot device (MSEL pin setting).
  • nConfig must not be issued when an HPS reset is in process.    If there is HPS reset in process,  wait for the HPS reset to finish before issuing nConfig  :   Greater than 10ms from time HPS reset is triggered.
  • If Intel Stratix 10 SoC Remote System Update is enabled on the device:  A boot failure during Phase 1 (re-)configuration can trigger a Remote System Update Watchdog event to trigger a reconfiguration event to recover the device.

Also see:  Why does my Intel Stratix 10 SoC design sometimes fail to detect a transition on hps_cold_nReset