Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Type: Answers

Area: Embedded


Last Modified: October 23, 2020
Version Found: v19.3
Bug ID: 18012283614
Document ID: S10-DATASHEET
Document Version Found: July 08, 2020

Why does my Intel Stratix 10 SoC design sometimes fail to detect a transition on hps_cold_nReset ?

Description

Due to problem in the Intel® Stratix® 10 Device Datasheet, the pulse width requirement on the Stratix 10  SDM HPS_cold_nReset  pin is not documented. 

Workaround/Fix

The pulse width requirement on the hps_cold_nReset pin is 3ms.

Note:

  • It is not required to cold reset the HPS if the intention is to reconfigure the device using the nConfig signal.  An nConfig event (reconfiguration) will wipe the entire device (HPS and FPGA), and then reconfigure the device  from the selected boot device (MSEL setting).
  •  nConfig must not be issued when an HPS reset in process.    If there is HPS reset in process,  wait for the HPS reset to finish before issuing nConfig  :   Greater than 10ms from time HPS reset is triggered.

Also see : 

  Why does my Intel Stratix 10 SoC device fail to boot / configure correctly, if I reset the HPS while a configuration event is taking place?