Device Family: Intel® Stratix® 10 SX

Type: Answers

Area: Embedded



Why does the Intel® Stratix® 10 Hard Processor System encounter an error while accessing the Secure Device Manager QSPI when the configuration clock source is set to the OSC_CLK_1 pin?

Description

Due to a problem in the U-Boot bootloader code, the Intel® Stratix® 10 Hard Processor System may report an error similar to the following when attempting to access the Secure Device Manager QSPI flash memory and the configuration clock source is set to the OSC_CLK_1 pin:

 

SOCFPGA_STRATIX10 # sf probe

SF: Calibration failed (low range)

SF: unrecognized JEDEC id bytes: ff, fc, 82

Failed to initialize SPI flash at 0:0 (error -2)

Workaround/Fix

To avoid this problem, set the configuration clock source to use the Internal Oscillator.  A fix for this issue is expected in a future update to the U-Boot bootloader code.