Device Family: Intel® Stratix® 10 SX

Type: Answers

Area: Embedded


Last Modified: October 18, 2018
Version Found: v18.1
Bug ID: FB: 559364;

Why does Intel® Stratix® 10 HPS UART / I2C / SPI peripheral run at the wrong speed or not work in Linux?

Description

Due to two different problems  UART, I2C and SPI IP on Intel® Stratix® 10 SoC FPGA Hard Processor System (HPS) devices may run at the wrong speed:

SoC FPGA Linux Kernels  4.17 and later (post June 2018) when a non default MPU clock frequency is used :  Fixed and patch uploaded to https://github.com/altera-opensource/linux-socfpga  commit 23d4f7b2c6000e095399a6266ef35c213f93649e

  • In SoC FPGA Linux 4.17 Kernels and later the Stratix 10 Clock Manager driver extracts the clocking information from the FPGA bitstream, and only the reference clock frequencies are specified in the device tree.     
  • Due to a problem some frequencies may be incorrect if the MPU frequency is set to a non default value 

SoC FPGA Linux Kernels  4.17 pre June 2018, and 4.16 and earlier:

  • The Linux Device Tree  contains information on the clocking structure of the Intel® Stratix® 10 SoC FPGA Hard Processor System (HPS),  and must reflect the clock setup in the Hard Processor System Intel Stratix 10  FPGA IP in the Intel® Quartus® Prime Pro Platform Designer system.  If the clocking structure is not updated to reflect your board and design,  peripherals may operate incorrectly in Linux.  Typical problems are UART or I2C interfaces working in u-boot,  but which do not work in Linux.
  • Due to a problem some frequencies may be incorrect if the MPU frequency is set to a non default value  (workaround below)

 

Workaround/Fix

SoC FPGA Linux Kernels  4.17 and later (post June 2018) when a non default MPU clock frequency is used

  • This problem is fixed for 4.18 kernel on https://github.com/altera-opensource/linux-socfpga  with  commit 23d4f7b2c6000e095399a6266ef35c213f93649e
  • A patch is also available to work around this issue 0002_clk-pll-s10_L3L4clockFrequencyFix_1.patch

Also see related KDB : Why does Linux fail to boot on my Intel® Stratix® 10 SoC when I use the f2s_free_clock as the HPS reference clock?

 

Soc FPGA Linux Kernels 4.17 pre June 2018 and 4.16 and earlier : 

See How  do I update the Linux Device Tree for Stratix 10 SX to match the Clock settings in Platform Designer? for information on how to update the Linux Device Tree to reflect the clocking settings in your design.

To work around the math error if non default MPU clock frequency is used

    - Manually set L3,L4 L4 Slow clock frequencies in the device tree

        ○ Leave the logic to describe the PLL's

        ○ Override the clocks from the L3 divider 

 

                l3_main_free_clk: l3_main_free_clk {

                    #clock-cells = <0>;

                    #compatible = "altr,socfpga-s10-perip-clk";

                    #clocks = <&noc_free_clk>;

                    #fixed-divider = <1>;

                    clock-frequency = <400000000>;

                    compatible = "fixed-clock"

                    

                };

 

                l4_sys_free_clk: l4_sys_free_clk {

                    #clock-cells = <0>;

                    #compatible = "altr,socfpga-s10-perip-clk";

                    #clocks = <&noc_free_clk>;

                    #fixed-divider = <4>;

                    clock-frequency = <100000000>;

                    compatible = "fixed-clock"

                    };

 

                l4_main_clk: l4_main_clk {

                    #clock-cells = <0>;

                    #compatible = "altr,socfpga-s10-gate-clk";

                    #clocks = <&noc_clk>;

                    clock-frequency = <400000000>;

                    compatible = "fixed-clock";

                    #div-reg = <0x70 0 2>;

                    #clk-gate = <0x30 1>;

                };

 

                l4_mp_clk: l4_mp_clk {

                    #clock-cells = <0>;

                    #compatible = "altr,socfpga-s10-gate-clk";

                    #clocks = <&noc_clk>;

                    clock-frequency = <200000000>;

                    compatible = "fixed-clock";

                    #div-reg= <0x70 8 2>;

                    #clk-gate = <0x30 2>;

                };

 

                l4_sp_clk: l4_sp_clk {

                    #clock-cells = <0>;

                    #compatible = "altr,socfpga-s10-gate-clk";

                    #clocks = <&noc_clk>;

                    clock-frequency = <100000000>;

                    compatible = "fixed-clock";

                    #div-reg= <0x70 16 2>;

                    #clk-gate = <0x30 3>;

                };