Due to two different problems UART, I2C and SPI IP on Intel® Stratix® 10 SoC FPGA Hard Processor System (HPS) devices may run at the wrong speed:
SoC FPGA Linux Kernels 4.17 and later (post June 2018) when a non default MPU clock frequency is used : Fixed and patch uploaded to https://github.com/altera-opensource/linux-socfpga commit 23d4f7b2c6000e095399a6266ef35c213f93649e
- In SoC FPGA Linux 4.17 Kernels and later the Stratix 10 Clock Manager driver extracts the clocking information from the FPGA bitstream, and only the reference clock frequencies are specified in the device tree.
- Due to a problem some frequencies may be incorrect if the MPU frequency is set to a non default value
SoC FPGA Linux Kernels 4.17 pre June 2018, and 4.16 and earlier:
- The Linux Device Tree contains information on the clocking structure of the Intel® Stratix® 10 SoC FPGA Hard Processor System (HPS), and must reflect the clock setup in the Hard Processor System Intel Stratix 10 FPGA IP in the Intel® Quartus® Prime Pro Platform Designer system. If the clocking structure is not updated to reflect your board and design, peripherals may operate incorrectly in Linux. Typical problems are UART or I2C interfaces working in u-boot, but which do not work in Linux.
- Due to a problem some frequencies may be incorrect if the MPU frequency is set to a non default value (workaround below)