Device Family: Intel® Stratix® 10 SX

Type: Answers, Errata

Area: Embedded, SoC FPGA Linux


Last Modified: December 06, 2018
Version Found: v18.1
Bug ID: FB: 610048;

Why does FPGA fabric (phase 2) configuration fail on my HPS Boot First Intel® Stratix® 10 SoC design?

Description

Due to a problem in the Intel® Quartus® Prime Pro software version 18.1,   phase 2 configuration of the FPGA fabric from the HPS  as part of a HPS boot first flow on Intel Stratix® 10 SoC devices may fail when run from u-boot or Linux  for large .RBF files.

Workaround/Fix

 

Patch 0.19 for the Intel® Quartus® Prime Pro software version 18.1 is available to fix this problem.   Download and install the patch from the relevant link below, recompile your Intel Quartus Prime Pro project and recreate programming file :

 

This fix is scheduled to be included in a future version of the Quartus Prime Pro Software