The HPS I2C controller supports SCL and SDA falling time configurable function.
Device Family: Intel® Arria® 10 SX, Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Intel® Stratix® 10 SX
About how to implement the configuration in linux OS, please refer to the link:https://github.com/altera-opensource/linux-socfpga/commit/7d0429364bf0c0e69bf192362d85076e6ee9abd7.
Designer can configure the SCL and SDA falling time parameter in dts file such as:
i2c-sda-falling-time-ns = <6000>; /* appended from boardinfo */
i2c-scl-falling-time-ns = <6000>; /* appended from boardinfo */
The SCL and SDA falling time configurable information will be added into Intel Arria 10 Hard Processor System Technical Reference Manual in a future release. Customer can refer the handbook Intel Arria 10 Hard Processor System Technical Reference Manual in future.