Article ID: 000086105 Content Type: Troubleshooting Last Reviewed: 01/04/2023

Is it possible to set SCL and SDA falling times of the HPS I2C controller independently?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The HPS I2C controller supports SCL and SDA falling time configurable function. 

    Resolution

    About how to implement the configuration in Linux OS, please refer to the link: https://github.com/altera-opensource/linux-socfpga/commit/7d0429364bf0c0e69bf192362d85076e6ee9abd7. 

    The designer can configure the SCL and SDA falling time parameters in dts file, such as:
       i2c-sda-falling-time-ns = <6000>; /* appended from boardinfo */
       i2c-scl-falling-time-ns = <6000>; /* appended from boardinfo */

    The SCL and SDA falling time configurable information has been added into the Intel Arria 10 Hard Processor System Technical Reference Manual .

    Related Products

    This article applies to 7 products

    Cyclone® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Intel® Arria® 10 SX SoC FPGA
    Intel® Stratix® 10 SX SoC FPGA

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