You may see this error message when the Arria® 10 SX BSP board.sys file is opened in Qsys and you choose the option “Sync All System Infos” using Quartus® Prime software version 17.0
Device Family: Intel® Arria® 10
This problem will be fixed in a future version of the Quartus® Prime software versions. To work around this issue then change "Address width" of pipe_stage_alt_pr and clock_cross_host_alt_pr to 6. Move address of clock_cross_host_alt_pr.s0 to 0xcf00 or 0xcf40.
If you recompile the base revision then this address change must also be reflected in the following file a10soc/arm32/driver/hw_mmd_constants.h by changing the ACL_PRCONTROLLER_OFFSET value to 0xcf40.