The HPS bridges can be enabled from the Preloader (SPL/MPL) or U-boot and in some cases from Linux.
The FPGA2SDRAM bridge FPGA port configuration is contained in the FPGA logic and before the bridge is enabled, the SDRAM subsystem must be put into an idle state and the FPGA port configuration must be applied.
- The SDRAM subsystem must be idle to avoid data loss on active transitions (HPS running from on-chip RAM, all peripherals disabled)
- If a new FPGA image is loaded the FPGA port configuration must be re-applied if the FPGA2SDRAM port configuration has changed.
Preloaders (SPL) and U-boot generated from SOC EDS 13.1 and later contain extra functionality and build in functions to safely enable the HPS bridges.