Device Family: Intel® Agilex™, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: June 15, 2020
Version Found: v18.1
Version Fixed: v20.3
Bug ID: 14011682749

Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1 and later,  you may see the “TCCS Report” in Timing Analyzer report an invalid value of 150ps when using the LVDS SERDES Intel® FPGA IP with Intel® Stratix® 10 and Intel® Agilex™ devices.

The correct value for both device families is 330ps.

Workaround/Fix

Check the respective device family datasheet for the correct TCCS information:

This problem is fixed starting with the Intel Quartus Prime Pro Edition software version 20.3.