Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1 and later,  you may see the “TCCS Report” in Timing Analyzer report an invalid value of 150ps when using the LVDS SERDES Intel® FPGA IP with Intel® Stratix® 10 and Intel® Agilex™ devices.

The correct value for both device families is 330ps.