Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: October 21, 2020
Version Found: v20.1
Version Fixed: v20.2
Bug ID: 14010875584

Why are the LVCMOS 3.3V or LVTTL 3.3V I/O Standards not available in Intel® Quartus® Prime Pin Planner or Assignment Editor for Intel® Stratix® 10 FPGAs 1SG040F35 and 1SX040F35?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1 and earlier, the LVCMOS 3.3V or LVTTL 3.3V I/O Standards are not available in Intel® Quartus® Prime Pin Planner or Assignment Editor for Intel® Stratix® 10 FPGA variants 1SG040F35 and 1SX040F35. 

Workaround/Fix

As a workaround, apply the LVCMOS 3.0V or LVTTL 3.0V I/O standard and connect VCCIO to 3.3V.

This problem is fixed starting with the Intel Quartus Prime Pro Edition software version 20.2. Once this fix is available, if using the workround above, it is recommended to recompile the design with the correct I/O standard setting.