Due to a problem in Intel® Quartus® Prime Pro Edition software version 20.3 and earlier, Active Serial configuration clock (AS_CLK) frequency is unexpectedly changed to 25MHz if QSPI_SET_CS command is used when the Mailbox Client Intel® FPGA IP or the Serial Flash Mailbox Client Intel® FPGA IP accesses a flash memory device when using Intel® Stratix® 10 devices.
AS_CLK frequency can be specified by Active serial clock source menu in Configuration category of Device and Pin Options dialog box. This setting should be applied to AS_CLK frequency for not only Active Serial configuration but also for those IPs operation, but once QSPI_SET_CS command is used, AS_CLK frequency is incorrectly changed to 25MHz. There is no way to revert AS_CLK frequncy back to the frequency specified in the Active Serial clock source menu.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Last Modified: October 16, 2020
Version Found: v20.3
Bug ID: 1508231819