Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: October 16, 2020
Version Found: v20.3
Bug ID: 1508231819

Why does the AS_CLK frequency unexpectedly change to 25MHz when the Mailbox Client Intel® FPGA IP or the Serial Flash Mailbox Client Intel® FPGA IP accesses a flash memory device when using Intel® Stratix® 10 devices?

Description

Due to a problem in Intel® Quartus® Prime Pro Edition software version 20.3 and earlier, Active Serial configuration clock (AS_CLK) frequency is unexpectedly changed to 25MHz if QSPI_SET_CS command is used when the Mailbox Client Intel® FPGA IP or the Serial Flash Mailbox Client Intel® FPGA IP accesses a flash memory device when using Intel® Stratix® 10 devices.
AS_CLK frequency can be specified by Active serial clock source menu in Configuration category of Device and Pin Options dialog box.  This setting should be applied to AS_CLK frequency for not only Active Serial configuration but also for those IPs operation, but once QSPI_SET_CS command is used, AS_CLK frequency is incorrectly changed to 25MHz.  There is no way to revert AS_CLK frequncy back to the frequency specified in the Active Serial clock source menu.

Workaround/Fix

To avoid this problem, do not use QSPI_SET_CS command.

Although the Mailbox Client Intel® FPGA IP User Guide and the Serial Flash Mailbox Client Intel® FPGA IP User Guide instruct to use QSPI_SET_CS command before one of the quad SPI operations, it is not necessary when only a flash device is connected to an Intel Stratix 10 device and the chip select of the flash device is connected to nCS[0] of the Intel Stratix 10 device.

There is no workaround when multiple flash devices are connected and QSPI_SET_CS command is required to select one of those flash devices.

This problem will be fixed in future version of Intel® Quartus® Prime Pro Edition software.