Device Family: Intel® Agilex™ Series, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: October 07, 2020
Version Found: v19.2
Version Fixed: v20.2
Bug ID: 1809200689

Why does the mgmt_waitrequest signal from the IOPLL Reconfig Intel FPGA not behave as expected when performing Dynamic Phase Shift in Intel® Stratix® 10 and Intel Agilex™ devices?

Description

Due to a known problem in Intel® Quartus® Prime Pro Edition software version 19.4 and earlier, the mgmt_waitrequest signal output from the IOPLL Reconfig Intel FPGA in Intel Stratix® 10 devices and Intel Agilex™ devices will operate in the opposite way that is described in the Intel® Stratix® 10 Clocking and PLL User Guide and Intel® Agilex™ Clocking and PLL User Guide by deasserting when Dynamic Phase Shift (DPS) is requested and asserting once completed.

Workaround/Fix

This problem is fixed starting with Intel Quartus Prime Pro Edition software version 20.2.