Device Family: Arria®

Device Family: Arria® II GX

Device Family: Intel® Cyclone®

Device Family: Intel® Cyclone® 10 LP

Device Family: Cyclone® II

Device Family: Cyclone® III

Device Family: Cyclone® IV

Device Family: Intel® Stratix®

Device Family: Stratix® II

Device Family: Stratix® III

Device Family: Stratix® IV

Intel Software: Quartus Prime Standard

Type: How-To

Area: Component


Last Modified: September 25, 2020
Version Found: v18.1
Bug ID: 1508274106

Why does reconfiguration using MIF/HEX file on ALTPLL_RECONFIG IP produce incorrect output clock frequency?

Description

When generating an output clock frequency with C-counter exceeding 512, a post-scale counter cascading is implemented. If you are generating a MIF/HEX from the ALTPLL IP where the C-counter exceeds 512, cascaded C-counter is not supported. After reconfiguration, you may see that output clock frequency is incorrect.

Workaround/Fix

Enable "Enter output clock parameters" in the ALTPLL IP and manually adjust the output clock parameters, and make sure C-counter does not exceed the value of 512 and the internal setting isn't injecting post-scale counter cascading, before generating the MIF/HEX file as shown below.

 

As an alternative, cascading of PLLs in normal or direct mode through the Global Clock (GCLK) network can be used to achive the desired output clock frequency.