Due to a problem with the Early Power Estimator (EPE) for Intel® Stratix® 10 devices version 19.4 and earlier, you may see this error even if there are still available pins when differential input pins are used and the VCCIO voltages of all I/O banks are not 2.5V.
Here is an example.
- Device: 1SG280H
- Package: F50
- Number of user I/O: 672
- Number of I/O bank: 14
- Number of pin pre I/O bank: 48
- User I/O usage:
- 1.2 V output * 625 pins
- LVDS input * 1 pair
In this case, since 625 pins are used for 1.2V output, the VCCIO voltages of 14 I/O banks are 1.2V.
LVDS input is powered by VCCPT, not VCCIO. So a pair of LVDS input should be able to be assigned to remaining pins. But the EPE for Intel Stratix 10 devices incorrectly displays an error like the following image.