When a RAM: 2-Port Intel® FPGA IP with the Emulated TDP dual clock mode parameter enabled is instantiated in the Intel® Quartus® Prime software, you might see a higher than expected FPGA resource utilization when targeting Intel Stratix® 10 devices. This is caused by the additional FIFOs implemented by the RAM: 2-Port Intel® FPGA IP.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Last Modified: June 19, 2019
Version Found: v17.1
Bug ID: 2205689125