Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: June 19, 2019
Version Found: v17.1
Bug ID: 2205689125

Why is there higher than expected FPGA resource utilization when instantiating the RAM: 2-Port Intel® FPGA IP with the Emulated TDP dual clock mode parameter enabled?

Description

When a RAM: 2-Port Intel® FPGA IP with the Emulated TDP dual clock mode parameter enabled is instantiated in the Intel® Quartus® Prime software, you might see a higher than expected  FPGA resource utilization when targeting Intel Stratix® 10 devices. This is caused by the additional FIFOs implemented by the RAM: 2-Port Intel® FPGA IP.

Workaround/Fix

To work around this problem, perform the following steps:

  1. Navigate through the hierarchy and find the fifo_wrapper_in instance.
  2. Move on through the hierarchy until you come across the dcfifo_component instance
  3. Reduce the value of the LPM_NUMWORDS and LPM_WIDTHU parameters. The value assigned for LPM_NUMWORDS must comply to the following equation: 2^LPM_WIDTHU. Make sure the FIFO depth is appropriate to support the data rate of your design.           

                 As an example:                

                    dcfifo_component.lpm_numwords  = 16                

                    dcfifo_component.lpm_widthu  = 4

Repeat steps from 1 to 3 for the fifo_wrapper_out instance.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.