Device Family: Intel® Stratix® 10
Last Modified: July 04, 2019
Version Found: v18.1
Version Fixed: v19.2
Bug ID: 1408427510
IP: Altera S10 Mailbox Client Core, Altera S10 Mailbox Client
The Intel® Stratix® 10 Mailbox Client IP may stop functioning or hang in the following scenarios :
1. Attempting to issue a write command while the write FIFO register is empty
2. Attempting to issue a write command while the write FIFO register has overflowed.
3. Attempting to send a write before setting the chip select.
If using Intel® Quartus® Prime Pro Edition Software version 19.1 and below, a power-cycle of the Intel® Stratix® 10 device is required to recover from this condition.
If using Intel® Quartus® Prime Pro Edition Software version 19.2 and above, scenario 1 and 2 can be recovered from by resetting the Intel® Stratix® 10 Serial Flash Mailbox Client IP. For scenario 3, an error message will be prompted if the device is configured with non ASx4 configuration scheme. However, QSPI_SET_CS command is optional if the device is configured with ASx4 configuration scheme.