Due to a problem in the Intel® Stratix® 10 device simulation model in the Intel® Quartus® Prime Pro Edition software version 19.1 and earlier, you may see unknown (x) MLAB RAM output values in gate-level simulation with the VHDL netlist (*.vho).
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro, Simulation
Last Modified: July 12, 2019
Version Found: v18.1
Bug ID: 1408971166