Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Simulation

Type: Answers

Area: Component


Last Modified: July 12, 2019
Version Found: v18.1
Bug ID: 1408971166

Why does the Intel® Stratix® 10 MLAB RAM generate unknown output values in gate-level simulation with a VHDL netlist?

Description

Due to a problem in the Intel® Stratix® 10 device simulation model in the Intel® Quartus® Prime Pro Edition software version 19.1 and earlier, you may see unknown (x) MLAB RAM output values in gate-level simulation with the VHDL netlist (*.vho). 

Workaround/Fix

To work around this problem, use the Verilog netlist (*.vo) for MLAB RAM in the gate-level simulation. 

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.