Intel® Stratix® 10 devices have additional clock requirements for successful configuration when Hard Processor System External Memory Interface (HPS EMIF), PCIe, eSRAM or High Bandwidth Memory (HBM2) is used.
The reference clocks are required for proper PLL calibration to ensure the aforementioned IP blocks can function properly when the device has completed configuration and entered user mode. The Secure Device Manager (SDM) firmware gates the device configuration if the PLL is not calibrated properly due to a missing reference clock. Thus, users must provide a free-running, stable reference clock to these IP blocks before configuration begins. The required reference clock for respective IP is stated below:
| IP | Clock Pin |
|---|---|
| HBM2 | pll_ref_clk and ext_core_clk |
| eSRAM | CLK_ESRAM_[0,1]p and CLK_ESRAM_[0,1]n |
| HPS EMIF | pll_ref_clk |
| L- and H-Tile PCIe Channels | REFCLK_GXB |
| E-Tile Transceivers Channels | REFCLK_GXE |
For Intel® Stratix® 10 L/H-tile devices, the reference clock requirement is mandatory for PCIe use case but not mandatory for non PCIe use case for a successful device configuration. For PCIe use case, the SDM firmware will wait for PLL calibration code to ensure the PLL is calibrated properly to release the device for entering user mode. Therefore, a reference clock is mandatory for PLL calibration. For non PCIe use case, without reference clock supply during configuration, SDM firmware will not gate device configuration without a proper PLL calibration code. Users can calibrate the transceiver PLL in user mode for transceiver channels to operate properly.
For Intel® Stratix® 10 E-tile devices, the reference clock requirement is mandatory for successful device configuration. The reference clock is required to load the configuration firmware into Intel® Stratix® 10 E-tile devices.