Device Family: Intel® Arria® 10, Arria® V, Intel® Cyclone® 10, Cyclone® IV, Cyclone® V, Intel® MAX® 10, Intel® Stratix® 10, Stratix® V

Type: Answers

Area: Component, Embedded

Last Modified: October 14, 2019
Version Found: v18.0 Update 1
Bug ID: 1808485146
Document ID: 1306878505

Why does a flash lock/unlock operation fail to work with the Intel® FPGA Generic Quad SPI Controller II IP?


You may see a failure to lock/unlock a flash sector while using the 'alt_qspi_controller2_lock' driver API in the Intel® FPGA Quad SPI Controller II Core. This is expected behavior if a Write Enable command is not issued before performing the lock/unlock instruction.

This is also known to impact the driver API for Intel FPGA Serial Flash Controller II Core.


To perform a successful lock/unlock to a flash sector, ensure the Write Enable instruction is issued prior to using the alt_qspi_controller2_lock or alt_epcq_controller2_lock driver API.

This is scheduled to be fixed in a later release of Intel Quartus® Prime Software.