Device Family: Intel® Stratix® 10

Type: Answers

Area: Component

Last Modified: August 16, 2019
Version Found: v18.1 Update 1
Bug ID: 1806852024
IP: Altera S10 Voltage Sensor, Altera S10 Mailbox Client Core, Altera S10 Temperature Sensor

Why does CvP Update fail after accessing the SDM Mailbox IPs in Intel® Stratix® 10 devices?


Due to a known problem in Intel® Quartus® Prime Pro Edition Software version 18.1 Update 1 and later, a Configuration via Protocol (CvP) Update on Intel Stratix® 10 devices could  fail if access to either an Intel Stratix 10 Temperature Sensor  / Intel Stratix 10 Voltage Sensor / Chip ID Intel Stratix 10 FPGA IP core / Stratix 10 Serial Flash Mailbox Client Intel FPGA IP core is performed before the subsequent core configuration. 


To work around this problem, either hold the SDM IP in reset for at least 1 second after the device enters user mode or remove the instance of the SDM IPs from your design .This is scheduled to be fixed in a future release of Intel Quartus Prime Pro Edition Software. 


See Related KDB

Why does reconfiguration of Intel® Stratix® 10 devices fail with designs containing an instance of any of the SDM Mailbox IPs?