Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component, EMIF


Last Modified: October 21, 2019
Version Found: v18.0
Version Fixed: v20.1
Bug ID: 1306751461

Why do I see an incorrect read latency when simulating the eSRAM Intel® Stratix® 10 FPGA IP?

Description

You may see an incorrect read latency when simulating the eSRAM Intel® Stratix® 10 FPGA IP because the IP instantiates a gate model CPA block for simulation, which can cause a hold violation at the PHY interface.

Workaround/Fix

 

To work around this in simulation, do the following.

1. Open  IP_generated_dir/esram_<>/sim/<>_esram_191_<>.sv

2. Search   defparam    fourteennm_cpa_component.pa_sim_mode    = "long"; 

3. Change to defparam    fourteennm_cpa_component.pa_sim_mode    = "short"; 

 

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.