You may see an incorrect read latency when simulating the eSRAM Intel® Stratix® 10 FPGA IP because the IP instantiates a gate model CPA block for simulation, which can cause a hold violation at the PHY interface.
Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX
Intel Software: Quartus Prime Pro
Area: Component, EMIF
Last Modified: October 21, 2019
Version Found: v18.0
Version Fixed: v20.1
Bug ID: 1306751461