Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Type: Answers

Area: Component

Last Modified: June 14, 2019
Version Found: v18.1 Update 2
Bug ID: 1807398508
IP: Altera IOPLL

Why do I observe an incorrect frequency from a cascaded IOPLL IP output in simulation?


You may see an incorrect frequency or behavior during simulation of cascaded IOPLL IP for Intel® Arria® 10, Intel Cyclone® 10 GX and Intel® Stratix® 10 devices.

This is due to a bug in the simple simulation model that is generated from the IOPLL IP by default.


To work around this, enable the PLL Auto Reset option in Physical PLL Settings before IOPLL IP generation.  This enables the advanced simulation  model which is not impacted by  this issue.

This problem is scheduled to be fixed in a future release of the Intel Quartus® Prime software