Article ID: 000074124 Content Type: Troubleshooting Last Reviewed: 04/21/2023

Why do I observe an incorrect frequency from a cascaded IOPLL IP output in simulation?

Environment

  • Intel® Quartus® Prime Pro Edition
  • IOPLL Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see an incorrect frequency or behavior during the simulation of cascaded IOPLL IP for Intel® Arria® 10, Intel Cyclone® 10 GX, and Intel® Stratix® 10 devices.

    This is due to a bug in the simple simulation model generated from the IOPLL IP by default.

    Resolution

    To work around this, enable the PLL Auto Reset option in Physical PLL Settings before IOPLL IP generation.  This enables the advanced simulation model, which is not impacted by this issue.

    This problem was fixed in Intel® Quartus® Prime Software version 22.1

     

     

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.