Due to a problem in Embedded Peripherals IP User Guide (UG-01085 | 2019.04.01), it mis-defined the RST bit counter control register as bit in Table 398. Counter Control Field Descriptions.
In fact, the RST bit should be bit.
You can reset all counters and statistics by writing bit of counter control register to 1.
Device Family: Intel® Arria® 10 GX, Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP, Cyclone® IV E, Intel® Stratix® 10 GX, Intel® Stratix® 10 TX
Intel Software: Quartus Prime Pro, Quartus Prime Standard
Last Modified: June 10, 2019
Version Found: v17.1
Bug ID: 1507231555
Document ID: UG-01085
Document Version Fixed: April 01, 2019