Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component, Tools


Last Modified: Fri Mar 22 2019 05:00:00 GMT-0700
Version Found: v18.0
Bug ID: 1807005335

What are the timing parameters for the External Host interface using Partial Reconfiguration in Intel® Stratix® 10 devices?

Description

If you intend to use External Host for Partial Reconfiguration in Intel® Stratix® 10 devices, use the Partial Reconfiguration External Configuration Controller Stratix 10 Intel FPGA IP. This IP reserves dedicated configuration pins for partial reconfiguration during user mode according to your configuration scheme.

If you choose Active Serial x4 Configuration scheme you must consider AS Configuration Timing parameters from Intel® Stratix® 10 Device Datasheet. 

If you choose AVST x8/16/32 Configuration scheme you must consider Avalon-ST Configuration Timing parameters from Intel® Stratix® 10 Device Datasheet.
 

Workaround/Fix