Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: October 04, 2019
Version Found: v19.3
Bug ID: 14010113819
Document ID: UG-S10SEU
Document Version Found: 19.2
Document Version Fixed: July 01, 2019

Is it possible to increase the Single Event Upset (SEU) error fifo depth when implementing the Advanced SEU Detection Intel® Stratix® 10 FPGA IP core in Off-Chip Lookup Sensitivity Processing mode?

Description

Yes, when instantiating the Advanced SEU Detection Intel® Stratix® 10 FPGA IP core you can use the SEU error fifo depth parameter to modify the size of the internal fifo. The value on this parameter will take effect in the two implementation modes supported by the IP: On-Chip Lookup Sensitivity Processing and Off-Chip Lookup Sensitivity Processing.

Workaround/Fix

This information is scheduled to be added in a future release of the Intel® Stratix® 10 SEU Mitigation User Guide.