Device Family: Intel® Stratix® 10

Type: Answers

Area: Component


Last Modified: November 08, 2019
Version Found: v19.3
Bug ID: 14010270221
IP: Altera IOPLL

How do I resolve the issue of an Intel® Stratix® 10 IOPLL not being able to obtain lock when the input refclk is driven by an output clock from the Intel Stratix 10 E-Tile?

Description

To resolve the issue of an Intel® Stratix® 10 IOPLL not being able to obtain lock when the input refclk is driven by an output clock from the Intel Stratix 10 E-Tile, you must perform user recalibration of the IOPLL once the output clocks from the Intel Stratix 10 E-Tile are stable.

Holding the Intel Stratix 10 IOPLL in reset until output clocks from the Intel Stratix 10 E-Tile are stable or pulsing the reset once the output clocks are stable will not resolve the Intel Stratix IOPLL unlocked state.

Workaround/Fix