Article ID: 000074174 Content Type: Product Information & Documentation Last Reviewed: 04/18/2023

How do I connect the RREF_SIPAUX pins on Intel® Stratix® 10 TX devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The RREF_SIPAUX pins have the same connection guidelines as other RREF pins on Intel® Stratix® 10 devices, and so should be connected to a 2-kΩ resistor (±1%) to GND.

Resolution

This problem is fixed starting with Intel® Stratix® 10 Device Family Pin Connection Guidelines version 2020.10.23.

Related Products

This article applies to 4 products

Intel® Stratix® 10 DX FPGA
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 NX FPGA
Intel® Stratix® 10 TX FPGA

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