In the Intel® Quartus® Prime Pro edition software version 19.1, this error message may be seen in designs that target Intel Stratix® 10 devices that include one or more instances of the LVDS SERDES Intel FPGA IP. This error may be reported while Fitter or Timing Analyzer stages are being executed.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Type: Answers
Area: Component
Last Modified: June 14, 2019
Version Found: v19.1
Bug ID: 2007805098
Error: LVDS SDC cannot find IOPLL. Ensure IOPLL SDC is listed before LVDS SDC in qsf.
Description
Workaround/Fix
To work around this problem, make sure that the IOPLL Intel FPGA IP is listed before the LVDS SERDES Intel FPGA IP in the 'IP Components' tab on the Intel Quartus Project Navigator. Alternatively, you can go to Assignments > Settings… , then choose 'Timing Analyzer' category and re-arrange the order of the IP files.
Once the order of the IP files is correct, proceed to install the following patch for your operating system:
- Download Intel® Quartus® Prime 19.1 Standard Edition patch 0.19 for Windows (.exe)
- Download Intel® Quartus® Prime 19.1 Standard Edition patch 0.19 for Linux (.run)
- Download ReadMe file for the Intel® Quartus® Prime 19.1 Standard patch 0.19 (.txt)
A fix is scheduled to be included on a future release of the Intel Quartus Prime Pro software.