In the Intel® Quartus® Prime Pro edition software version 19.1, this error message may be seen in designs that target Intel Stratix® 10 devices that include one or more instances of the LVDS SERDES Intel FPGA IP. This error may be reported while Fitter or Timing Analyzer stages are being executed.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Last Modified: June 14, 2019
Version Found: v19.1
Bug ID: 2007805098