Device Family: Intel® Stratix® 10

Type: Answers

Area: Component


Last Modified: December 14, 2019
Version Found: v19.3
Bug ID: 2209985219

Can an Intel® Stratix® 10 High-Speed LVDS I/O interface be dynamically set to a different data rate or phase shift?

Description

An Intel® Stratix® 10 High-Speed LVDS I/O interface can be set to a different data rate or phase shift, but only if the Use External PLL option is selected in the LVDS SERDES Intel® FPGA IP core parameter editor. If this option is not selected, changing the data rate or phase shift might cause the Dynamic Phase Alignment (DPA) circuitry to fail to lock, even if the correct reset and initialization sequence is followed.

Refer to Intel® Stratix® 10 High-Speed LVDS I/O User Guide, section 3.1.7 for more information on the Use External PLL mode, and section 4.2.2 for more information on the reset and initialization sequence.

Workaround/Fix