Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component

Last Modified: September 05, 2019
Version Found: v19.1
Bug ID: 2205699867

** Warning: ../ip_ad_lvds/altera_lvds_core14_181/sim/ (vlog13233) Design unit "ip_ad_lvds_altera_lvds_core14_181_ibrwinq" already exists and will be overwritten. Overwriting a VHDL entity with a Verilog module.


Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1,  you may see the above mentioned warning in the ModelSim* GUI when using Intel® Stratix® 10 LVDS SERDES IP.


There is no workaround for this issue.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.