Due to a problem in the Intel® Stratix® 10 devices listed below, if it takes longer than 18 seconds from the completion of power up to the configuration of the first 256 Kb of configuration bitstream your Stratix® 10 device may fail to configure.
The root cause lies in the Boot ROM, which causes a watchdog timer to overflow and causes the device to hang. This issue applies to all configuration schemes. Configuration via Protocol (CvP) is not impacted if the programming of the periphery meets the 18 seconds requirement as described in the workaround. This issue does not apply to reconfiguration.
If you are using the Intel FPGA Download Cable II and you encounter this issue, you will see the following error message: Error (20068): Configuration error, you must power-cycle the device to recover from this condition. To avoid this error, you must ensure that the device is configured within 18 seconds after completion of the power-on sequence.
This issue affects the following Intel Stratix 10 devices:
Impacted Stratix 10 GX variants
- Intel Stratix 10 GX 1100 H-Tile ES1
- Intel Stratix 10 GX 2800 H-Tile ES2
- Intel Stratix 10 GX 2800 H-Tile ES3
- Intel Stratix 10 GX 2800 L-Tile ES3
- Intel Stratix 10 GX 2500 L-Tile Production
- Intel Stratix 10 GX 2800 L-Tile Production
Impacted Stratix 10 SX variants
- Intel Stratix 10 SX 1100 H-Tile ES1
- Intel Stratix 10 SX 2800 L-Tile ES1
- Intel Stratix 10 SX 2800 L-Tile ES2
- Intel Stratix 10 SX 2800 L-Tile ES3
- Intel Stratix 10 SX 2800 H-Tile ES3
Impacted Stratix 10 MX variants
- Intel Stratix 10 MX 2100 H-Tile ES1
Impacted Stratix 10 TX variants
- Intel Stratix 10 TX 2800 ES1
- Intel Stratix 10 TX 2100 ES1