Device Family: Intel® Stratix® 10

Type: Answers

Area: Component


Last Modified: August 13, 2018
Version Fixed: v18.0 Update 1
Bug ID: FB: 554283, 560628;
IP: Altera S10 Mailbox Client Core

Why does the Avalon MM master hang when issuing a read request to the Mailbox Client Intel® Stratix® 10 FPGA IP?

Description

The Mailbox Client Intel® Stratix® 10 FPGA IP contains some Write-Only registers which do not return any read data when the Avalon MM master issues a read request to them. Hence the Avalon MM master can hang if it is waiting for a response from the Mailbox Client Intel Stratix 10 FPGA IP. A write to Read-Only registers won’t cause any issue since Avalon MM supports posted write that does not wait for write completion response. This issue can happen on any Avalon MM master for example, JTAG to Avalon Master Bridge IP or Nios II processor that supports both read and write requests.

Workaround/Fix

This issue is fixed in Intel Quartus® Prime Pro software version 18.0.1.